1 data sheet acquired from harris semiconductor schs165e features asynchronous master reset ?, k, (d) inputs to first stage fully synchronous serial or parallel data transfer shift right and parallel load capability complementary output from last stage buffered inputs typical f max = 50mhz at v cc = 5v, c l = 15pf, t a = 25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30%of v cc at v cc = 5v pinout cd54hc195 (cerdip) cd74hc195 (pdip, soic, sop, tssop) top view description the device is useful in a wide variety of shifting, counting and storage applications. it performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. the two modes of operation, shift right (q 0 -q 1 ) and parallel load, are controlled by the state of the parallel enable ( pe) input. serial data enters the ?st ?p-?p (q 0 ) via the j and k inputs when the pe input is high, and is shifted one bit in the direction q 0 -q 1 -q 2 -q 3 following each low to high clock transition. the j and k inputs provide the ?xibility of the jk- type input for special applications and by tying the two pins together, the simple d-type input for general applications. the device appears as four common-clocked d ?p-?ps when the pe input is low. after the low to high clock transition, data on the parallel inputs (d0-d3) is transferred to the respective q 0 -q 3 outputs. shift left operation (q 3 -q 2 ) can be achieved by tying the q n outputs to the dn-1 inputs and holding the pe input low. all parallel and serial data transfers are synchronous, occurring after each low to high clock transition. the ?c195 series utilizes edge triggering; therefore, there is no restriction on the activity of the j, k, pn and pe inputs for logic operations, other than set-up and hold time requirements. a low on the asynchronous master reset ( mr) input sets all q outputs low, independent of any other input condition. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 mr j k d0 d1 d2 gnd d3 v cc q 1 q 2 q 3 q 3 cp pe q 0 ordering information part number temp. range ( o c) package CD54HC195F3A -55 to 125 16 ld cerdip cd74hc195e -55 to 125 16 ld pdip cd74hc195m -55 to 125 16 ld soic cd74hc195nsr -55 to 125 16 ld sop cd74hc195pw -55 to 125 16 ld tssop cd74hc195pwr -55 to 125 16 ld tssop cd74hc195pwt -55 to 125 16 ld tssop note: when ordering, use the entire part number. the suf? r denotes tape and reel. the suf? t denotes a small-quantity reel of 250. september 1997 - revised october 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc195, cd74hc195 high-speed cmos logic 4-bit parallel access register [ /title ( cd74 h c195 ) / sub- j ect ( high s peed c mos l ogic 4 -bit p aral- l el a ccess r egis- t er) / autho
2 functional diagram truth table operating modes inputs output mr cp pe j kdnq 0 q 1 q 2 q 3 q 3 asynchronous reset l xxxxx llllh shift, set first stage h hhhx h q 0 q 1 q 2 q 2 shift, reset first stage h hl lxlq 0 q 1 q 2 q 2 shift, toggle first stage h hh l x q 0 q 0 q 1 q 2 q 2 shift, retain first stage h hlhxq 0 q 0 q 1 q 2 q 2 parallel load h lxxdnd 0 d 1 d 2 d3 d2 h = high voltage level l = low voltage level, x = don? care = transition from low to high level l = low voltage level one set-up time prior to the low to high clock transition h = low voltage level one set-up time prior to the high to low clock transition, dn (q n ) = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the low to high clock transition. 11 q 3 1 2 10 3 j cp k mr 15 14 13 12 94567 q 0 q 1 q 2 q 3 d 0 d 1 d 2 d 3 pe cd54hc195, cd74hc195
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) package thermal impedance, ja (see note 1): e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 o c/w m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 o c/w ns (sop) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 o c/w pw (tssop) package . . . . . . . . . . . . . . . . . . . . . . . . . 108 o c/w maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 a cd54hc195, cd74hc195
4 prerequisite for switching function parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min max min max min max clock frequency f max - 26-5-4-mhz 4.5 30 - 25 - 20 - mhz 6 35 - 29 - 23 - mhz mr pulse width t w - 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 614-17-20-ns clock pulse width t w - 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 614-17-20-ns set-up time j, k, pe to clock t su - 2 100 - 125 - 150 - ns 4.5 20 - 25 - 30 - ns 617-21-26-ns hold time j, k, pe to clock t h - 23-3-3-ns 4.53-3-3-ns 65-3-3-ns removal time, mr to clock t rem - 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 614-17-20-ns switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units typ max max max hc types propagation delay, cp to output t plh , t phl c l = 50pf 2 - 175 220 265 ns 4.5 - 35 44 53 ns 6 - 30 37 45 ns propagation delay, mr tooutput t plh , t phl c l = 50pf 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 33 38 ns output transition times (figure 1) t tlh , t thl c l = 50pf 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns input capacitance c in ---1010 10pf cp to q n propagation delay t plh , t phl c l = 15pf 5 14 - - - ns mr to q n t phl c l = 15pf 5 13 - - - ns maximum clock frequency f max c l = 15pf 5 50 - - - mhz power dissipation capacitance (notes 2, 3) c pd c l = 15pf 45 - - - pf notes: 2. c pd is used to determine the dynamic power consumption, per flip-flop. 3. p d =v cc 2 f i + (c l v cc 2 +f o ) where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. cd54hc195, cd74hc195
5 test circuit and waveforms figure 1. clock prerequisite and propagation delays and output transition times figure 2. master reset prerequisite and propagation delays figure 3. j, k, or parallel enable prerequisite times clock q or q v cc gnd t thl t tlh 10% 90% l/f max t w t r t f v s t plh t phl 10% 90% 0.5 v cc reset q t plh q clock t rem v s t phl v s t w v cc gnd v cc gnd 0.5 v cc 0.5 v cc pe, k valid j 0.5 v cc t su clock v s v cc gnd gnd t h cd54hc195, cd74hc195
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) CD54HC195F3A active cdip j 16 1 tbd a42 snpb n / a for pkg type cd74hc195e active pdip n 16 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hc195ee4 active pdip n 16 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hc195m active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195m96 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195m96e4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195me4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195nsr active so ns 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195nsre4 active so ns 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195pw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195pwe4 active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195pwre4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195pwt active tssop pw 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc195pwte4 active tssop pw 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. package option addendum www.ti.com 6-dec-2006 addendum-page 1
important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 6-dec-2006 addendum-page 2
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2006, texas instruments incorporated
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